Renesas Completes Design of CPU Core for Next-Generation Microcontrollers
November 14, 2007 // Published as a news service by IHS
| |
| IHS Parts Solutions |
| Source parts, manage obsolescence, comply with regulations and speed time-to-market. For more information and a price quote, please complete the form below. |
|
Renesas Technology Corp. completed the design of a new complex instruction set computer (CISC) central processing unit (CPU) architecture that it said will deliver unmatched capabilities in code efficiency, processing performance and power consumption for a future generation of Renesas CISC microcontrollers (MCUs).
Products based on this architecture will be branded as the RX family and will be targeted at office automation, digital consumer electronics and industrial system applications.
The RX family will be the first to use the Renesas eXtreme MCU core. RX devices will be built around 16 b and 32 b versions of the new CPU.
Characteristics of the RX architecture are as follows:
- Maximum operating frequency: 200 MHz.
- Processing performance: 1.25 MIPS/MHz (Dhrystone v2.1 benchmark).
- High code efficiency: 30% reduction in object-code size compared with existing products.
- Low power consumption: 0.03 mA/MHz.
- Compatibility and scalability with existing CISC products.
The first of the enhanced MCUs are expected to become available in 2Q 2009.
Other features include:
- High-performance CPU. The new CPU is based on a Harvard architecture, which provides separate address and data paths, allowing the execution of instructions and data access in single cycle. This single-cycle capability was tested and verified using field-proven Renesas MCUs, the company said. As a result, the new architecture is optimized with the use of registers, instructions and address modes. It has 16 32 b general-purpose registers, which allow the CPU to process both data and addresses in all available registers.
- On-chip floating point unit. To enable real-time control and multimedia applications, the RX CPU incorporates functions such as multiply, divide and multiply/accumulate. It also implements an Institute of Electrical & Electronics Engineers (IEEE) 754 compliant 32 b single-precision floating-point processing unit (FPU) for handling multiple data types. The FPU reduces the calculation time for data processing tasks, the number of cycles needed for mathematical calculations and the response time for any event occurrence, Renesas said.
- Efficient use of code. The RX CPU core has 4 GB of address space and supports 12 types of address modes including register indirect with index and post increment. The new CPU core supports byte-unit variable-length execution instructions that range from 1 B to 9 B. It assigns 1 B or 2 B instructions to the most frequently used functions. Renesas said it expects that the new core will be 30% more code efficient compared with existing Renesas devices.
- Low power consumption. The newly developed 90 nanometer (nm) process that will be used to build the MCU with the RX architecture is a low-power, low-current-leakage technology. The new architecture can achieve 0.03 mA/MHz or less power consumption at active mode when the CPU is running at full speed.
- Compatibility and scalability. To provide customers upgrade paths for higher-performance MCUs or other compatible devices, Renesas said it plans to offer a suite of development tools for all devices with the RX architecture. The new tool chain including a C compiler will ensure the reuse of code, protecting customers' investments made in the H8 and M16C families, Renesas said.
Source: Renesas Technology Corp.