Altera Offers Nios II Embedded Evaluation Kit with FPGA Design Capabilities

November 28, 2007 // Published as a news service by IHS

The Nios II evaluation kit platform provides a hands-on way for embedded designers to assess the Nios II processor, system on a programmable chip (SOPC) builder system design software and their custom applications.

The kit combines a Cyclone III starter board and a touch screen liquid crystal display (LCD) in a Plexiglas case. Developers can use it to launch example applications, such as networking, audio and image processing, with the touch of a finger.

The kit also serves as a development platform for software designers new to field-programmable gate array (FPGA) based processors.

The kit includes the Nios II embedded design suite (EDS) and several tutorials and design examples (with source code). Ten design examples from Altera and several embedded partners are included with the kit to demonstrate the benefits of designing with FPGAs.

These examples include hardware acceleration of image processing applications and a remote FPGA update design that shows how FPGA developers can update hardware designs over the Internet to add new product features or deliver bug fixes.

The embedded evaluation kit includes the following memory and input/output (I/O) interfaces:

• 3C25 FPGA with 25 K logic elements.
• 32 MB double-data-rate synchronous dynamic random access memory (DDR SDRAM).
• 1 MB synchronous static RAM (SSRAM).
• 16 MB Flash.
• 10/100 Ethernet (physical layer [PHY].
• 800 x 480 color touch panel LCD.
• Secure digital (SD) card interface (I/F) (with SD Flash card).
• Audio output and input.
• Microphone input.
• Composite video input.
• Video graphics array (VGA) output.
• Personal system 2 (PS2) interface.
• Recommended standard 232 (RS-232).

The kit also includes cables and accessories, a Nios II evaluation kit CD-ROM (with software tutorials and examples) and the Altera design suite DVD.

Source: Altera Corp.