Xilinx Releases Free Reference Design, IP for Development of SFI-5 Applications

March 13, 2008 // Published as a news service by IHS

The SFI-5 interface enables communication between the optical transmission devices and the network processing system.

Based on 65 nanometer (nm) Xilinx Virtex-5 LX330T field-programmable gate arrays (FPGAs), the reference design accelerates the development of wired networking systems requiring 40 Gbps payload rates, Xilinx said.

This enables applications using transport interfaces like OC768/STM256 and optical transport network (OTN) optical channel transport unit 3 (OTU-3) in systems such as optical cross connects, fiber optics terminators and repeaters, 40 G multiplexers, and test equipment.

The reference design has been hardware verified on the Xilinx ML525 evaluation platform and characterized for skew, temperature, process and voltage variations to ensure reliable interface, compatible with the OIF SFI-5 standard, Xilinx said.

This Virtex-5 LXT FPGA-based reference design uses 17 transceivers (16 for data and one for calibration).

"Networking equipment is rapidly moving to 40 G payload rates where SFI-5 provides the chip-to-chip interface to the optical transponders," said Anil Telikepalli, senior manager of platform solutions marketing at Xilinx.

"The Virtex-5 LXT FPGA platform is ideal for implementing the SFI-5 physical layer, as well as additional logic blocks such as forward error correction and framer. The hardware-verified SFI-5 reference design takes advantage of the industry's only 65 nm FPGA in production today with built-in low-power transceivers, providing generous deskew margin on the receiver side for sustained operation under changing system conditions," Telikepalli said.

The free reference design for SFI-5 interface is available for download at http://www.xilinx.com/spi_sfi.

The Virtex-5 LX330T FPGA is available now, and the ML525 development board will be available in May 2008.

Source: Xilinx Inc.