Xilinx: Digital Front-End Design to Spur Development of 3GPP LTE Radios
November 29, 2008 // Published as a news service by IHS
Xilinx Inc. announced availability of a complete digital front end (DFE) design it says is optimized for faster, lower-cost development of third generation partnership protocol (3GPP) long-term evolution (LTE) wireless communications systems.
According to Xilinx, it is the industry's first DFE design targeted for high-performance 3GPP LTE radio applications that reduces overall power consumption and is scalable from large multisector macrocell to picocell base stations.
The Xilinx 3GPP LTE design supports a programmable development platform using Xilinx Virtex-5 field programmable gate arrays (FPGAs).
The LTE DFE platform consists of optimized blocks for digital up conversion (DUC), digital down conversion (DDC) and crest factor reduction (CFR) that together form a complete LTE radio subsystem, according to the company.
It is compatible with existing digital predistortion (DPD) designs from Xilinx, enabling systems architects to develop and integrate all the digital system elements of a high-performance, commercial LTE system, and in a shorter period of time than is feasible with traditional application-specific standard part (ASSP) and application-specific IC circuit (ASIC) design methods, Xilinx said.
"LTE is set to be the dominant wireless standard over the coming years, and developers need to ensure that they have products available for operator trials within a small window of opportunity, and this window is rapidly closing," said David Hawke, senior product manager of radio and wireless interfaces for Xilinx.
"Our DFE reference design makes it easier for designers to leverage the systems knowledge, support and optimization skills that Xilinx has developed, and apply it to their own 3GPP LTE product developments, saving significant engineering costs, lowering total system power consumption and accelerating their delivery timescales," Hawke said.
Xilinx said the LTE DFE design is highly configurable and has been built to support dual carrier 5 and 10 MHz bandwidths, four carrier 5 MHz bandwidth and seven single and multicarrier implementations, including single carrier 5, 10, 15 and 20 MHz bandwidths.
Designers can select an implementation based on their system requirements, without paying a penalty on design area and reducing overall system cost and power, Xilinx said. The Xilinx system generator for DSP tool suite also can be used to customize designs to meet the needs of company-specific 3GPP-LTE radio applications.
Source: Xilinx Inc.