Renesas to Release Low-Power SRAM for Consumer, Automotive, Communications Applications
March 31, 2008 // Published as a news service by IHS
Renesas Technology Corp. announced the development of the R1WV6416R series of 64 Mb advanced low-power static random access memory (SRAM) (advanced LPSRAM) products and the R1LV3216R series of 32 Mb advanced LPSRAM products with compact chip size.
They will be available in different packages and specifications, such as access time, for a total of 12 64 Mb products and eight 32 Mb products to meet a range of requirements in fields including industry, office equipment, consumer electronics, automotive systems and communications equipment.
Sample shipments of the 32 Mb products will begin in April 2008, and the 64 Mb products will begin shipping in July, in Japan.
Renesas said these two new series will extend its lineup of advanced LPSRAM products employing exclusive memory cell technology to achieve smaller chip sizes and soft error free.
The features of the R1WV6416R series and R1LV3216R series include the following:
- LPSRAM with capacity of 64 Mb. The new products each comprise a stack of two compact 32 Mb advanced LPSRAM chips in a single package. They meet demand for larger-capacity LPSRAM for high-performance systems and meet reduced space requirements in applications that would have required multiple LPSRAM devices, Renesas said.
- Different packages to meet a range of requirements. To accommodate a variety of applications, these two new series are being offered in several different packages: thin small-outline package I (TSOP I) (48 pin), µTSOP (52 pin) and for 64 Mb products fine-pitch ball grid array (FBGA) (48 ball).
The TSOP I and µTSOP packages have the same dimensions as those of previous 16 Mb products, and the ball layout of the FBGA package is signal pin compatible. According to Renesas, this enables customers to increase memory capacity while continuing to use their existing layout designs.
- Soft error free and latchup free features. Advanced LPSRAM uses a stacked capacitor memory cell configuration. According to Renesas, it virtually eliminates soft errors caused by alpha radiation or high-energy neutron radiation, which can be a problem with ultrafine SRAM. In addition, this memory cell configuration avoids the unintended formation of a parasitic thyristor, which can generate spurious current flows and cause latchups.
The R1WV6416R series and the R1LV3216R series products are available with access times of 55 nanoseconds (ns) or 70 ns.
Source: Renesas Technology Corp.