Fujitsu Launches SD Multidecoder LSI for Expanding H.264 SD Broadcasts
December 8, 2008 // Published as a news service by IHS
Fujitsu Microelectronics Ltd. launched multidecoder large-scale integration (LSI) chips that support decoding of Moving Picture Experts Group 2 (MPEG-2) and ITU H.264 video compression formats for standard definition (SD) video, in particular for SD digital broadcasts in Russia, Eastern Europe and China.
Sample shipments of the new MB86H01 series will start from Dec. 1, 2008.
According to Fujitsu, these system LSIs are suited for TV and set-top-box (STB) equipment targeted for the Russian, Eastern European and China markets.
These products support the digital video broadcasting (DVB) standard used in those regions, with MPEG-2 and ITU H.264 decoders integrated into a single chip with the functionality necessary for receiving SD broadcasts.
The LSIs use proprietary ITU H.264 decoder technology for low power consumption and feature small packaging. They can be used in portable devices like personal navigation devices (PND) with built-in TV receivers.
The DVB digital broadcasting standard is used in Europe and Russia and by some broadcast systems in China. For SD broadcasting, the MPEG-2 compression format is used; however, it is expected that the next-generation compression format ITU H.264 will ramp up in Eastern Europe including Russia, Fujitsu said. Also, the ITU H.264 format is used in some cable TV services in China for interactive video on demand (VoD).
With the shift of SD broadcasting to the ITU H.264 format in Russia, Eastern Europe, China, and elsewhere, TVs and STBs for these regions need to be able to handle decoding of both MPEG-2 and ITU H.264 formats, Fujitsu said. Targeting such markets, Fujitsu Microelectronics is offering the MB86H01 series, which consists of two SD multidecoder LSI products (MB86H01 AA/MB86H01 AB) that support both MPEG-2 and ITU H.264 formats.
The new LSI multidecoders include the functionality needed for TVs and STBs to process SD digital broadcasts, including two MPEG-2 decoders and one ITU H.264 decoder.
The dual MPEG-2 decoders can process two video streams that can be used in digital video recorders (DVRs) with twin tuners. They also allow viewing of two programs at the same time with picture in picture.
A high-speed universal serial bus (USB) 2.0 on the go (OTG) controller is also integrated, giving connectivity to external devices, such as digital cameras.
These LSIs integrate into a single chip a 202.5 MHz ARC Tangent-A4 central processing unit (CPU) together with the necessary video and audio decode functions, as well as screen display functionality needed to receive digital broadcasts.
The MB86H01 series offers a 27 millimeter by 27 millimeter plastic ball grid array (PBGA) package with 256 pins, as well as a 10 millimeter by 10 millimeter fine-pitch ball grid array (FBGA) package with 240 pins for use in portable devices with built-in TV receivers.
This LSI has package and pin compatibility with the existing SmartMPEG-C series and maintains architectural compatibility, allowing current SmartMPEG users to upgrade or develop their systems, Fujitsu said.
Source: Fujitsu.