Fujitsu Launches HD H.264 CODEC LSIs for Portable Devices, Home Networked Appliances
November 5, 2008 // Published as a news service by IHS
Fujitsu Microelectronics Ltd. announced two new large-scale integrations (LSIs) to expand its line-up of ITU H.264 coder-decoder (CODEC) LSIs that encode and decode full high-definition (HD) (1,920 dots x 1,080 lines) video in the H.264 format.
The products are targeted at recording, playing and transmitting HD video on portable devices such as digital camcorders, as well as on home networked appliances, commercial broadcast equipment and security cameras.
The first of the two products to be launched, the MB86H55, features power consumption of 500 mW during full HD encoding including the in-package memory. Sample shipments of the MB86H55 will start in January 2009.
In addition, the LSI, MB86H56, will offer processing of full HD video at 60 frames per second (progressive), 60 p, to improve picture quality even further, Fujitsu said. Samples shipments of the MB86H56 will start from April 2009.
The two new products have memory in-package to offer a package size of 15 millimeters by 15 millimeters.
These two new products, as well as the existing MB86H51 CODEC LSI, use Fujitsu Laboratories' proprietary picture quality algorithm.
Both LSIs feature small form-factor and low power consumption necessary for portable devices, Fujitsu said.
They contain one 512 M bit memory (fast cycle random access memory [FCRAM]) in-package. Due to the reduction in the number of memory chips, as well as the usage of 65 nanometer (nm) process technology, the power consumption during full HD encoding, including the in-package memory, is reduced to 500 mW (at 30 frames per second).
Both products have an embedded scaler for expansion or reduction of the picture. In units of 16 b by 32 lines, pictures can be expand by a maximum of six times or reduced to 1/6, therefore accommodating the requirements for picture quality, resolution and bit rate depending on the application.
Both products also contain interfaces for improved connectivity. For the host interface to connect to an external central processing unit (CPU), there is a 16 b parallel interface and a transport stream (TS) interface as the video stream interface.
In addition, there is a serial interface in which a reduction of pins for host interface is possible, as well as a peripheral component interconnect (PCI) interface for connecting a PC or a recorder. Connection to external read-only memory (ROM) is also possible.
Source: Fujitsu.