Fujitsu Develops CMOS Logic-Based High-Voltage Transistor for Power Amplifiers

December 31, 2008 // Published as a news service by IHS

Fujitsu developed a 45 nanometer (nm) generation CMOS-based transistor that handles 10 volt (V) power output.

Fujitsu said this enables the transistor to handle high-output requirements necessary for power amplifiers used in Worldwide Interoperability for Microwave Access (WiMAX) and other high-frequency applications.

The new technology makes it possible for power amplifiers to be formed on the same die as CMOS logic control circuitry to achieve single-chip integration.

Because power amplifiers for wireless devices demand high power output at high frequencies, currently compound semiconductors such as gallium-arsenide (GaAs) are commonly used, mounted as a chip separate from control circuitry based on a general-purpose CMOS logic chip.

According to Fujitsu, integrating these chips' functions onto a single chip would enable cost reduction of the overall module and speed adoption of wireless devices to be used with wireless communication standards such as WiMAX and Long Term Evolution (LTE).

However, the power output required of power amplifiers for use in high-frequency applications, such as WiMAX, exceeds the breakdown voltage of transistors used with standard CMOS logic processes.

Overcoming this hurdle while remaining compatible with CMOS process technology requires an increase in the transistor's breakdown voltage, which is achieved with a structure that lowers the electric field around the drain, as electric fields can lead to transistor failure.

Furthermore, structures with high breakdown voltages typically increase the transistor's on-resistance, making it difficult to obtain satisfactory performance at high frequencies, Fujitsu said. Therefore, any tool would need to both raise breakdown voltage and avoid increasing on-resistance.

The transistor's drain is surrounded by a lightly doped drain (LDD) region, which overlaps with the gate. This lowers the electrical field extending horizontally to the drain, and the electrical field extending to the gate oxide layer, thereby raising the breakdown voltage, according to the company.

The dopant distribution in the transistor channel follows a lateral gradient. This lowers the density of dopant on the drain side of the channel, thus limiting the increase in drain resistance, which is the main part of on-resistance. It also lowers the electrical field extending horizontally to the drain, also raising the breakdown voltage.

The typical method for raising the breakdown voltage of a CMOS transistor has been to widen the gap separating gate and drain. This new structure suppresses on-resistance effectively compared with the conventional method, without increasing the gap, Fujitsu said.

Furthermore, Fujitsu said it believes this new structure to be compatible with standard transistors with 3.3 V input/output (I/O), since it requires only the additional steps of forming the LDD region and the custom channel region.

By using 45 nm process technology to apply the new transistor's technology to standard transistors with 3.3 V I/O, Fujitsu developed a transistor that raises the breakdown voltage from 6 V to 10 V.

Power output of 0.6 watt (W) per gate width of 1 millimeter (0.6 W/mm) was reached at maximum oscillation frequency of 43 GHz, demonstrating sufficient performance for use as a power transistor in WiMAX, Fujitsu said. According to the company, the new transistor also produced good results in basic reliability testing.

Source: Fujitsu.